MC68HC11KW1 Datasheet, PDF (178/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.3.2 T3OC1–T3OC3 — Timer 3 output compare registers
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer 3 output compare 1 (T3OC1)
high
$0094 (bit 15)
(14)
(13)
(12)
(11)
(10)
(9) (bit 8) 1111 1111
Timer 3 output compare 1 (T3OC1) low $0095 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
Timer 3 output compare 2 (T3OC2)
high
$0096 (bit 15)
(14)
(13)
(12)
(11)
(10)
(9) (bit 8) 1111 1111
Timer 3 output compare 2 (T3OC2) low $0097 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
Timer 3 output compare 3 (T3OC3)
high
$0098 (bit 15)
(14)
(13)
(12)
(11)
(10)
(9) (bit 8) 1111 1111
Timer 3 output compare 3 (T3OC3) low $0099 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
These three output compare registers are 16-bit read-write. Each is initialized to $FFFF at reset.
If an output compare register is not used for an output compare function, it can be used as a
storage location. A write to the high-order byte of an output compare register pair inhibits the
output compare function for one bus cycle. This inhibition prevents inappropriate subsequent
comparisons. Coherency requires a complete 16-bit read or write. However, if coherency is not
needed, byte accesses can be used.
For output compare functions, write a comparison value to output compare registers
T3OC1–T3OC3 and TI1/O4. When the TCNT3 value matches the comparison value, specified pin
actions occur.
9 _9.3.3
TCNT3 — Timer 3 counter register
Timer 3 count (TCNT3) high
Timer 3 count (TCNT3) low
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0092 (bit 15) (14) (13) (12) (11) (10) (9) (bit 8) 0000 0000
$0093 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 0000 0000
This register can be read at any time. In normal modes (SMOD = 0), writing any value to the
counter causes it to be rest to $0000. In special modes (SMOD = 1), any write to the most
significant byte (MSB) causes the counter to be preset to $FFF8.This preset capability is intended
for factory testing only. The counter can be stopped and reset by writing to the T3STP bit in the
TCTL6 register (see Section 9.3.5).
The 16-bit read-only TCNT3 register contains the value of the 16-bit timer. A full counter read
addresses the most significant byte (MSB) first. A read of this address causes the less significant
byte (LSB) to be latched into a buffer for the next CPU cycle so that a double-byte read returns the
full 16-bit state of the counter at the time of the MSB read cycle.
TCNT3 resets to $0000.
9-26
TIMING SYSTEM
MC68HC11KW1