MC68HC11KW1 Datasheet, PDF (65/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

4.3.2.8 TCTL4 and TCTL6 — Timer 2 and 3 control registers
Timer control register 4 (TCTL4)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0081 EDGB EDGA PR2B PR2A ECEB ECEA T2STP I1/04 0000 0000
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer control register 6 (TCTL6) $0091 EDGB EDGA PR3B PR3A ECEB ECEA T3STP I1/04 0000 0000
4
Bits [5:2] in both these registers can be written only once after reset. The following paragraphs describe
the Timer 2 control bits in TCTL4; the Timer 3 control bits in TCTL6 are described in Section 9.
EDGB and EDGA — Input capture edge control (Refer to Section 9)
This pair of bits configures the input capture edge detector circuits for IC1. IC1 functions only if
the I1/O4 bit is set.
PR2A and PR2B — Timer 2 prescaler select
These bits are used to select the prescaler divide-by ratio for Timer 2. They can be written to only
once after reset.
PR2B
0
0
1
1
PR2A
0
1
0
1
Prescaler
1
4
8
16
PR3A and PR3B — Timer 3 prescaler select
These bits are used to select the prescaler divide-by ratio for Timer 3. They can only be written to
once after reset. If PR3B and PR3A are both cleared, then Timer 3 is synchronized to the
prescaled Timer 1 rate.
PR3B
0
0
1
1
PR3A
0
1
0
1
Prescaler
Use Timer 1 rate
1
4
16
MC68HC11KW1
OPERATING MODES AND ON-CHIP MEMORY
4-21