MC68HC11KW1 Datasheet, PDF (172/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.2.6 TCNT2 — Timer 2 counter register
Timer 2 count (TCNT2) high
Timer 2 count (TCNT2) low
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0082 (bit 15) (14) (13) (12) (11) (10) (9) (bit 8) 0000 0000
$0083 (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 0000 0000
This 16-bit register can be read at any time. In normal modes (SMOD = 0), writing any value to
the counter causes it to be reset to $0000. In special modes (SMOD = 1), any write to the most
significant byte (MSB) causes the counter to be preset to $FFF8. This preset capability is intended
for factory testing only. The counter can be stopped and reset by writing to the T2STP bit in the
TCTL4 register (see Section 9.2.8).
The TCNT2 register contains the value of the 16-bit timer. A full counter read addresses the most
significant byte (MSB) first. A read of this address causes the less significant byte (LSB) to be
latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state
of the counter at the time of the MSB read cycle.
TCNT2 resets to $0000.
9.2.7 TCTL3 — Timer control register 3 (Timer 2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
9
Timer control register 3 (TCTL3) $0080 OM1 OL1 OM2 OL2 OM3 OL3 OM4 OL4 0000 0000
The bits of this register specify the action taken as a result of a successful Timer 2 OCx compare.
OM[1:4] — Output mode
OL[1:4] — Output level
OMx OLx Action taken on successful compare
0
0 Timer disconnected from OCx pin logic
0
1 Toggle OCx output line
1
0 Clear OCx output line to 0
1
1 Set OCx output line to 1
These control bit pairs are encoded to specify the action taken after a successful OCx compare.
OC4 functions only if the I1/O4 bit in the TCTL4 register is clear.
9-20
TIMING SYSTEM
MC68HC11KW1