MC68HC11KW1 Datasheet, PDF (60/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

ADPU — A/D power-up (refer to Section 10)
1 (set) – A/D system power enabled.
0 (clear) – A/D system disabled, to reduce supply current.
After enabling the A/D power, at least 100µs should be allowed for system stabilization.
CSEL — Clock select (refer to Section 10)
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1 (set) – A/D and EEPROM use internal RC clock source (about 1.5MHz).
0 (clear) – A/D and EEPROM use system E clock (must be at least 1MHz).
This bit selects the clock source for the on-chip EEPROM and A/D charge pumps. The on-chip RC
clock should be used when the E clock frequency falls below 1MHz.
IRQE — Configure IRQ for falling-edge-sensitive operation
1 (set) – Falling-edge-sensitive operation.
0 (clear) – Low-level-sensitive operation.
DLY — Enable oscillator start-up delay
1 (set) – A stabilization delay of around 4064 bus cycles is imposed as the
MCU is started up from STOP mode (or power-on reset).
0 (clear) –
The oscillator start-up delay is bypassed and the MCU resumes
processing within about four bus cycles. A stable external oscillator
is required if this option is selected.
DLY is set on reset, so a delay is always imposed as the MCU is started up from power-on reset.
CME — Clock monitor enable (refer to Section 5)
1 (set) – Clock monitor enabled.
0 (clear) – Clock monitor disabled.
In order to use both STOP and clock monitor, the CME bit should be cleared before executing
STOP, then set after recovering from STOP.
FCME — Force clock monitor enable (refer to Section 5)
1 (set) – Clock monitor enabled; cannot be disabled until next reset.
0 (clear) – Clock monitor follows the state of the CME bit.
When FCME is set, slow or stopped clocks will cause a clock failure reset sequence. To utilize
STOP mode, FCME should always be cleared.
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OPERATING MODES AND ON-CHIP MEMORY
MC68HC11KW1