MC68HC11KW1 Datasheet, PDF (29/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

The DWOM bit in SPCR disables the p-channel output drivers of pins D[5:2], and the WOMS bit
in SCCR1 disables those of pins D[1,0]. Because the n-channel driver is not affected by DWOM
or WOMS, setting either bit causes the corresponding port D pins to become open-drain-type
2
outputs suitable for wired-OR operation. In wired-OR mode (PORTD bits at logic level zero), the
pins are actively driven low by the n-channel driver. When a port D bit is at logic level one, the
associated pin is in a high impedance state as neither the n-channel nor the p-channel devices
are active. It is customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port D can be configured for wired-OR operation when the MCU is in single chip or
expanded mode.
For further information, refer to Section 6, Section 7 (SCI) and Section 8 (SPI).
2.11.5 Port E
Port E pins can be used as the analog inputs for the analog-to-digital converter, or as
general-purpose inputs. For further information, refer to Section 6 and Section 10 (A/D).
2.11.6 Port F
Port F is an 8-bit, general-purpose I/O port with a data register (PORTF) and a data direction
register (DDRF). In single chip mode, port F pins are general purpose I/O pins (PF[7:0]). In
expanded mode, port F pins act as the low-order address lines (ADDR[7:0]) of the address bus.
PORTF can be read at any time and always returns the pin level. If PORTF is written, the data is
stored in internal latches. The pins are driven only if they are configured as outputs in single chip
or bootstrap mode.
Port F pins include on-chip pull-up devices that can be enabled or disabled via the port pull-up
assignment register (PPAR). For further information, refer to Section 6.
2.11.7 Port G
In normal modes, Port G is an 8-bit general-purpose port with 6 I/O lines (PG[5:0]), and two input
only lines (PG[7, 6]). Associated with port G are a data register (PORTG), a data direction register
(DDRG) and an assignment register (PGAR). Pins [7, 6] can be used as general-purpose inputs,
or as inputs to the analog-to-digital converter. The functions of pins [5:0] are controlled by bits in
the port G assignment register (PGAR), which select whether the pins are used for general
purpose I/O, or, in expanded mode, for the memory expansion lines XA[18:13].
PORTG can be read at any time and always returns the pin level. If PORTG is written, the data is
stored into an internal latch. The pin is driven only if it is configured as an output.
Pins [5:0] have on-chip pull-up devices that can be enabled or disabled via the port pull-up
assignment register (PPAR). Refer to Section 6, Section 10 (A/D) and Section 4.
MC68HC11KW1
PIN DESCRIPTIONS
2-9