MC68HC11KW1 Datasheet, PDF (36/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

3.1.6.6 Half carry (H)
The H-bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an
ADD, ABA, or ADC instruction. Otherwise, the H-bit is cleared. Half carry is used during BCD
3
operations.
3.1.6.7 X interrupt mask (X)
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is set by default
and must be cleared by a software instruction. When an XIRQ interrupt is recognized, the X- and
I-bits are set after the registers are stacked, but before the interrupt vector is fetched. After the
interrupt has been serviced, an RTI instruction is normally executed, causing the registers to be
restored to the values that were present before the interrupt occurred. The X interrupt mask bit is
set only by hardware RESET or XIRQ acknowledge). X is cleared only by program instruction
(TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value loaded into the CCR from
the stack has been cleared). There is no hardware action for clearing X.
3.1.6.8 Stop disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from putting the M68HC11 into a
low-power stop condition. If the STOP instruction is encountered by the CPU while the S-bit is set,
it is treated as a no-operation (NOP) instruction, and processing continues to the next instruction.
S is set by reset — STOP disabled by default.
3.2
Data types
The M68HC11 CPU supports the following data types:
• Bit data
• 8-bit and 16-bit signed and unsigned integers
• 16-bit unsigned fractions
• 16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A word is composed of two
consecutive bytes with the most significant byte at the lower value address. Because the
M68HC11 is an 8-bit CPU, there are no special requirements for alignment of instructions or
operands.
CENTRAL PROCESSING UNIT
MC68HC11KW1
3-6