MC68HC11KW1 Datasheet, PDF (181/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.3.6 T3MSK — Timer 3 interrupt mask register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer 3 interrupt mask (T2MSK) $009C OC1I OC2I OC3I C4I TO2I 0
0
0 0000 0000
Use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts.
Note:
Bits in T3MSK correspond bit for bit with flag bits in T3FLG. Ones in T3MSK enable the
corresponding interrupt sources.
OC1I–OC3I — Output compare x interrupt enable
1 (set) – OCx interrupt is enabled.
0 (clear) – OCx interrupt is disabled.
If an OCxI enable bit is set when its associated OCxF flag bit is set, a hardware interrupt sequence is
requested. These three bits and the C4I bit are associated with a single Timer 3 output compare
interrupt sequence; any successful output compare or input capture causes such an interrupt unless
the corresponding OCxI or C4I bit is clear. Therefore flag polling is required if more than one interrupt
is enabled.
C4I— Input capture 1/output compare 4 interrupt enable
1 (set) – IC1/OC4 interrupt is enabled.
0 (clear) – IC1/OC4 interrupt is disabled.
9
When I1/O4 in TCTL4 is set, C4I is the input capture 1 interrupt enable bit.
When I1/O4 in TCTL4 is zero, C4I is the output compare 4 interrupt enable bit.
TO3I — Timer 3 overflow interrupt enable
1 (set) – Timer 3 overflow interrupt requested when T3OF is set.
0 (clear) – T3OF interrupts disabled.
Bits [2:0] — Not implemented; always read zero.
MC68HC11KW1
TIMING SYSTEM
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