MC68HC11KW1 Datasheet, PDF (66/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

ECEB and ECEA — Event counter edge control
These control bits configure the input clock source for the Timer 2 counter. They can be written to
only once after reset.
ECEB ECEA
Configuration
0
0
Timer 2 uses internal clock and prescaler
0
1
Count on rising edges of external clock only
4
1
0
Count on falling edges of external clock only
1
1
Count on any edge of external clock
T2STP — Stop Timer 2 counter (Refer to Section 9)
1 (set) – Timer 2 counter and prescaler are stopped and the counter is reset
to $0000.
0 (clear) – Timer 2 counter operates normally.
I1/O4 — Input capture 1/output compare 4 (Refer to Section 9)
1 (set) – Input capture 1 function is enabled (no OC4).
0 (clear) – Output compare 4 function is enabled (no IC1).
4.4
Memory expansion
4.4.1 Memory expansion logic
The MC68HC11KW1 has the ability to extend the address range of the M68HC11 CPU beyond
the physical 64K byte limit of the 16 CPU address lines. The extra addressing capability is provided
by a register-based paging scheme using expansion address lines and the physical 64K bytes of
CPU address space.
Two additional on-chip blocks are provided with the MC68HC11KW1. The first block implements
additional address lines that become active only when required by the CPU. The second block
provides chip-select signals that simplify the interface to external peripheral devices. Both of these
blocks are fully programmable by values written to associated control registers.
4-22
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11KW1