MC68HC11KW1 Datasheet, PDF (152/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

LSBF — LSB first enable
1 (set) – SPI data is transferred LSB first.
0 (clear) – SPI data is transferred MSB first.
If this bit is set, data, which is usually transferred MSB first, is transferred LSB first. LSBF does not
affect the position of the MSB and LSB in the data register. Reads and writes of the data register
always have MSB in bit 7.
SPR2 — SPI clock rate select
When set, SPR2 adds a divide-by-4 prescaler to the SPI clock chain. With the two bits in the
SPCR, this bit specifies the SPI clock rate. Refer to Table 8-1.
XDV[1, 0] — XOUT clock divide select (refer to Section 4)
These two bits control the frequency of the XCLK signal, which is output on the XOUT pin if
enabled by the CLKX bit in CONFIG.
8
8-10
SERIAL PERIPHERAL INTERFACE
MC68HC11KW1