MC68HC11KW1 Datasheet, PDF (102/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Table 5-4 Interrupt and reset vector assignments
Vector address
Interrupt source
CCR Local
mask bit mask
FFC0, C1 – FFCA, CB • Reserved
—
—
FFCC, FFCD •Timer 3 overflow
I
TO3I
•Timer 3 input capture 1/output compare 4
C4I
FFCE, FFCF
•Timer 3 output compare 1
•TImer 3 output compare 2
I
OC1I
OC2I
•Timer 3 output compare 3
OC3I
FFD0, FFD1 Timer 2 overflow
I
TO2I
FFD2, FFD3 Timer 2 input capture 1/output compare 4 I
C4I
5
FFD4, D5
•Timer 2 output compare 1
•Timer 2 output compare 2
OC1I
I
OC2I
•Timer 2 output compare 3
OC3I
FFD6, D7
• SCI receive data register full
• SCI receiver overrun
• SCI transmit data register empty
• SCI transmit complete
• SCI idle line detect
RIE
RIE
I
TIE
TCIE
ILIE
FFD8, D9
SPI serial transfer complete
I
SPIE
FFDA, DB
Pulse accumulator input edge
I
PAII
FFDC, DD
Pulse accumulator overflow
I PAOVI
FFDE, DF
Timer 1 overflow
I
TOI
FFE0, E1
Timer 1 input capture 4/output compare 5 I I4/O5I
FFE2, E3
Timer 1 output compare 4
I
OC4I
FFE4, E5
Timer 1 output compare 3
I
OC3I
FFE6, E7
Timer 1 output compare 2
I
OC2I
FFE8, E9
Timer 1 output compare 1
I
OC1I
FFEA, EB
Timer 1 input capture 3
I
IC3I
FFEC, ED
Timer 1 input capture 2
I
IC2I
FFEE, EF
Timer 1 input capture 1
I
IC1I
FFF0, F1
Real-time interrupt
I
RTII
FFF2, F3
IRQ pin
I
None
FFF4, F5
XIRQ pin
X None
FFF6, F7
Software interrupt
None None
FFF8, F9
Illegal opcode trap
None None
FFFA, FB
COP failure
None
NOCO
P
FFFC, FD
Clock monitor fail
None CME
FFFE, FF
RESET
None None
5-12
RESETS AND INTERRUPTS
MC68HC11KW1