MC68HC11KW1 Datasheet, PDF (187/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.6.1 PACTL — Pulse accumulator control register
Address bit 7
Pulse accumulator control (PACTL) $0026 0
bit 6 bit 5 bit 4 bit 3
PAEN PAMOD PEDGE 0
bit 2
bit 1
bit 0
State
on reset
I4/O5 RTR1 RTR0 0000 0000
Four of this register’s bits control an 8-bit pulse accumulator system. Another bit enables either
the OC5 function or the IC4 function, while two other bits select the rate for the real-time interrupt
system.
Bits [7, 3] — Not implemented; always read zero
PAEN — Pulse accumulator system enable
1 (set) – Pulse accumulator enabled.
0 (clear) – Pulse accumulator disabled.
PAMOD — Pulse accumulator mode
1 (set) – Gated time accumulation mode.
0 (clear) – Event counter mode.
PEDGE — Pulse accumulator edge control
This bit has different meanings depending on the state of the PAMOD bit, as shown:
PAMO
D
PEDGE
Action of clock
9
0
0 PAI falling edge increments the counter.
0
1 PAI rising edge increments the counter.
1
0 A zero on PAI inhibits counting.
1
1 A one on PAI inhibits counting.
I4/O5 — Input capture 4/output compare 5
1 (set) – Input capture 4 function is enabled (no OC5).
0 (clear) – Output compare 5 function is enabled (no IC4).
RTR[1:0] — RTI interrupt rate selects (refer to Section 9.4)
MC68HC11KW1
TIMING SYSTEM
9-35