MC68HC11KW1 Datasheet, PDF (144/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

8.2
SPI transfer formats
During an SPI transfer, data is simultaneously transmitted and received. A serial clock line
synchronizes shifting and sampling of the information on the two serial data lines. A slave select
line allows individual selection of a slave SPI device; slave devices that are not selected do not
interfere with SPI bus activities. On a master SPI device, the select line can optionally be used to
indicate a multiple master bus contention. Refer to Figure 8-2.
MCU
system clock
Divider
÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128
8-bit shift register
Read data buffer
Shift control logic
8
Select
SPI clock (master)
Clock
logic
OPT2 – Options register 2
SPI control
MSTR
SPE
SPIE
S
MISO
PD2
M
M
MOSI
S
PD3
Pin
control
logic
S
SCK
M
PD4
SS
PD5
SPSR – SPI status register
SPI interrupt
request
SPCR – SPI control register
Internal bus
SPDR – SPI data register
Figure 8-1 SPI block diagram
SERIAL PERIPHERAL INTERFACE
MC68HC11KW1
8-2