MC68HC11KW1 Datasheet, PDF (146/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

8.3.1 Master in slave out
MISO is one of two unidirectional serial data signals. It is an input to a master device and an output
from a slave device. The MISO line of a slave device is placed in the high-impedance state if the
slave device is not selected.
8.3.2 Master out slave in
The MOSI line is the second of the two unidirectional serial data signals. It is an output from a
master device and an input to a slave device. The master device places data on the MOSI line a
half-cycle before the clock edge that the slave device uses to latch the data.
8.3.3 Serial clock
SCK, an input to a slave device, is generated by the master device and synchronizes data
movement in and out of the device through the MOSI and MISO lines. Master and slave devices
are capable of exchanging a byte of information during a sequence of eight clock cycles.
There are four possible timing relationships that can be chosen by using control bits CPOL and CPHA
in the serial peripheral control register (SPCR). Both master and slave devices must operate with the
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same timing. The SPI clock rate select bits, SPR[1:0], in the SPCR of the master device, select the
clock rate. In a slave device, SPR[1:0] have no effect on the operation of the SPI.
8.3.4 Slave select
The slave select SS input of a slave device must be externally asserted before a master device
can exchange data with the slave device. SS must be low before data transactions begin and must
stay low for the duration of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault error flag (MODF) is set
in the serial peripheral status register (SPSR). To disable the mode fault circuit, write a one in bit
5 of the port D data direction register. This sets the SS pin to act as a general-purpose output,
rather than a dedicated input to the slave select circuit, thus inhibiting the mode fault flag. The
other three lines are dedicated to the SPI whenever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS. CPHA settings should
be identical for master and slave. When CPHA = 0, the shift clock is the OR of SS with SCK. In
this clock phase mode, SS must go high between successive characters in an SPI message.
When CPHA = 1, SS can be left low between successive SPI characters. In cases where there is
only one SPI slave MCU, its SS line can be tied to V_SS as long as only CPHA = 1 clock mode is
used.
SERIAL PERIPHERAL INTERFACE
MC68HC11KW1
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