MC68HC11KW1 Datasheet, PDF (94/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

5.1.5 OPTION — System configuration options register 1
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
System config. options 1 (OPTION) $0039 ADPU CSEL IRQE DLY CME FCME CR1 CR0 0001 0000
The special-purpose OPTION register sets internal system configuration options during
initialization. The time protected control bits (IRQE, DLY, FCME and CR[1:0]) can be written to only
once in the first 64 cycles after a reset and then they become read-only bits. This minimizes the
possibility of any accidental changes to the system configuration. They may be written at any time
in special modes.
5
ADPU — A/D power-up (refer to Section 10)
1 (set) – A/D system power enabled.
0 (clear) – A/D system disabled, to reduce supply current.
CSEL — Clock select (refer to Section 10)
1 (set) – A/D and EEPROM use internal RC clock (about 1.5MHz).
0 (clear) – A/D and EEPROM use system E clock (must be at least 1MHz).
IRQE — Configure IRQ for falling-edge-sensitive operation (refer to Section 4)
1 (set) – Falling-edge-sensitive operation.
0 (clear) – Low-level-sensitive operation.
DLY — Enable oscillator start-up delay (refer to Section 4)
1 (set) – A stabilization delay is imposed as the MCU is started up from STOP
mode (or from power-on reset).
0 (clear) –
The oscillator start-up delay is bypassed and the MCU resumes
processing within about four bus cycles. A stable external oscillator
is required if this option is selected.
Note:
Because DLY is set on reset, a delay is always imposed as the MCU is started up from
power-on reset.
CME — Clock monitor enable
1 (set) – Clock monitor enabled.
0 (clear) – Clock monitor disabled.
RESETS AND INTERRUPTS
MC68HC11KW1
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