MC68HC11KW1 Datasheet, PDF (203/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

ADCTL register is again written. Each time the ADCTL register is written, this bit is automatically
cleared, any current conversion is aborted and a new conversion sequence is started.
CONV8 — Convert 8/convert 4 select bit
1 (set) – Convert 8 channels or one channel 8 times, (uses all 8 result
registers).
0 (clear) – Convert 4 channels or one channel 4 times (uses 4 result registers).
SCAN — Continuous scan control
1 (set) – Convert continuously.
0 (clear) – Perform selected number of conversions (4 or 8) and stop.
MULT — Multiple channel/single channel control
1 (set) – Convert the channels in the selected group.
0 (clear) – Convert single channel selected.
CD, CC, CB, CA — Channel select bits
When 4-conversion (CONV8 = 0) and multiple channel (MULT=1) modes are selected, the CB and
CA bits have no meaning or effect, and the CD and CC bits specify which of four groups of four
channels are to be converted. When 8-conversion (CONV8 = 1) and multiple channel (MULT=1)
modes are selected, the CC, CB and CA bits have no meaning or effect. Refer to Table 10-1 for a
list of the A/D channel assignments.
10.7.2 ADFRQ — A/D converter frequency select register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
A/D frequency select register (ADFRQ) $0032 0
0
0
0
0
0
0 ADER 0000 0000
10
This register can be read and written at any time.
Bits [7:1] — Not implemented; always read zero.
ADER — A/D frequency select
1 (set) – E/2 clock is used for A/D conversions.
0 (clear) – E clock is used for A/D conversions.
This bit improves the accuracy of conversion when the MC68HC11KW1 bus frequency is above
2.1MHz.
MC68HC11KW1
ANALOG-TO-DIGITAL CONVERTER
10-7