MC68HC11KW1 Datasheet, PDF (26/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

2.9
VRH and VRL
2
These pins provide the reference voltages for the analog-to-digital converter.
2.10
R/W
In expanded and test modes, R/W performs the read/write function. R/W signals the direction of
transfers on the external data bus. A high on this pin indicates that a read cycle is in progress.
In single chip mode the R/W signal is driven low.
2.11
Port signals
The MC68HC11KW1 includes 80 pins that are arranged into ten 8-bit ports (A, B, C, D, E, F, G, H,
J and K). All the port pins are bidirectional, except for PG7, PG6 and port E pins [7:0]; these are
input only. Most of the bidirectional ports serve a purpose other than I/O, depending on the
operating mode or peripheral function selected. The input-only pins may be used as
general-purpose inputs, or as inputs to the A/D converter. Note that ports B, C, and F are available
for I/O functions only in single chip and bootstrap modes. Refer to Table 2-1 for details of the port
signals’ functions in different operating modes.
Note:
When using the information about port functions, do not confuse pin function with the
electrical state of the pin at reset. All general purpose I/O pins configured as inputs at
reset are in a high-impedance state. Port data registers reflect the functional state of
the port at reset. The pin function is mode dependent.
2.11.1 Port A
Port A is an 8-bit, general-purpose I/O port with a data register (PORTA) and a data direction
register (DDRA). Port A pins share functions with the main 16-bit timer system, Timer 1 (see
Section 9 for further information). PORTA can be read at any time and always returns the pin level.
If written, PORTA stores the data in internal latches. The pins are driven only if they are configured
as outputs. Writes to PORTA do not change the pin state when the pins are configured for timer
output compares.
Out of reset, port A pins [7:0] are general purpose high-impedance inputs. When the functions
associated with these pins are disabled, the bits in DDRA govern the I/O state of the associated
pin. For further information, refer to Section 6.
PIN DESCRIPTIONS
MC68HC11KW1
2-6