MC68HC11KW1 Datasheet, PDF (100/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

8) Timer 1 input capture 2
9) Timer 1 input capture 3
10) Timer 1 output compare 1
11) Timer 1 output compare 2
12) Timer 1 output compare 3
13) Timer 1 output compare 4
14) Timer 1 input capture 4/output compare 5
15) Timer 2 output compare 1, 2, 3
16) Timer 2 input capture 1/output compare 4
17) Timer 1 overflow
5
18) Timer 2 overflow
19) Pulse accumulator overflow
20) Pulse accumulator input edge
21) Timer 3 capture/compare
22) Timer 3 overflow
23) SPI transfer complete
24) SCI system
Any one of these maskable interrupts can be assigned the highest maskable interrupt priority by
writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise, the priority
arrangement remains the same. An interrupt that is assigned highest priority is still subject to
global masking by the I-bit in the CCR, or by any associated local bits. Interrupt vectors are not
affected by priority assignment. To avoid race conditions, HPRIO can only be written while I-bit
interrupts are inhibited.
5.3.1 HPRIO — Highest priority I-bit interrupt and misc. register
Highest priority interrupt (HPRIO)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$003C RBOOT SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
RBOOT, SMOD, and MDA bits depend on power-up initialization mode and can only be written in
special modes when SMOD = 1. Refer to Table 4-4.
RBOOT — Read bootstrap ROM (refer to Section 4)
1 (set) – Bootloader ROM enabled, at $BE40–$BFFF.
0 (clear) – Bootloader ROM disabled and not in map.
5-10
RESETS AND INTERRUPTS
MC68HC11KW1