MC68HC11KW1 Datasheet, PDF (84/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

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4-40
Table 4-18 Chip select control parameter summary
CSIO (I/O chip select)
Enable IOEN in CSCTL — 1 = On, OFF at reset (0)
Valid IOCSA in CSCTL — 1 = Address valid, 0 = E high
Polarity IOPL in CSCTL — 1 = Active high, 0 = Active low
Size
IOSZ in CSCTL —
1 = 4K ($1000–$1FFF)
0 = 8K ($0000–$1FFF)
Start address Fixed (see Size above)
Stretch IO1SA:IO1SB in CSCSTR — 0, 1, 2, or 3 E clocks
CSPROG (program chip select)
Enable PSCEN in CSCTL — 1 = On, ON at reset
Valid Fixed (Address valid)
Polarity Fixed (Active low)
PCSZA:PCSZB — 0:0 = 64K ($0000–$FFFF)
Size
in CSCTL
0:1 = 32K ($8000–$FFFF)
1:0 = 16K ($C000–$FFFF)
1:1 = 8K ($E000–$FFFF)
Start address Fixed (see Size above)
Stretch PCSA:PCSB in CSCSTR — 0, 1, 2, or 3 E clocks
Priority
GCSPR in CSCTL — 1 = CSGPx above CSPROG
0 = CSPROG above CSGPx
CSGP1, CSGP2 (general purpose chip selects)
Enable Set size to 0K bytes to disable
Valid Refer to GPCS1C / GPCS2C — Address valid or E high
Polarity Refer to GPCS1C / GPCS2C — Active high or low
Refer to GPCS1C / GPCS2C — 2K to 512K in nine
Size steps, 0K bytes = disable, can also follow memory
expansion window 1 or window 2
Start address Refer to GPCS1A / GPCS2A
Stretch Refer to CSCSTR — 0, 1, 2, or 3 E clocks
Other G1DG2 in GPCS1C allows CSGP1 and CSGP2 to be
logically OR'ed and driven out the CSGP2 pin.
G1DPC in GPCS1C allows CSGP1 and CSPROG to
be logically OR'ed and driven out the CSPROG pin.
G2DPC in GPCS2C allows CSGP2 and CSPROG to
be logically OR'ed and driven out the CSPROG pin.
MXGS2 in MMSIZ allows CSGP2 to follow either 64K
CPU addresses or 512K expansion addresses.
MXGS1 in MMSIZ allows CSGP1 to follow either 64K
CPU addresses or 512K expansion addresses.
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11KW1