MC68HC11KW1 Datasheet, PDF (130/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

7.1
Data format
The serial data format requires the following conditions:
– An idle-line condition before transmission or reception of a message.
– A start bit, logic zero, transmitted or received, that indicates the start of each
character.
– Data that is transmitted and received least significant bit (LSB) first.
– A stop bit, logic one, used to indicate the end of a frame. (A frame consists
of a start bit, a character of eight or nine data bits, and a stop bit.)
– A break (defined as the transmission or reception of a logic zero for some
multiple number of frames).
Selection of the word length is controlled by the M bit of SCCR1.
7.2
Transmit operation
7
The SCI transmitter includes a parallel data register (SCDRH/SCDRL) and a serial shift register.
The contents of the shift register can only be written through the parallel data register. This double
buffered operation allows a character to be shifted out serially while another character is waiting
in the parallel data register to be transferred into the shift register. The output of the shift register
is applied to TXD as long as transmission is in progress or the transmit enable (TE) bit of serial
communication control register 2 (SCCR2) is set. The block diagram, Figure 7-2, shows the
transmit serial shift register and the buffer logic at the top of the figure.
7.3
Receive operation
During receive operations, the transmit sequence is reversed. The serial shift register receives
data and transfers it to the parallel receive data registers (SCDRH/SCDRL) as a complete word.
This double buffered operation allows a character to be shifted in serially while another character
is still in the serial data registers. An advanced data recovery scheme distinguishes valid data from
noise in the serial data stream. The data input is selectively sampled to detect receive data, and
majority sampling logic determines the value and integrity of each bit.
SERIAL COMMUNICATIONS INTERFACE
MC68HC11KW1
7-2