MC68HC11KW1 Datasheet, PDF (192/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.7.2.2 Clock prescaler selection
The three available clocks are clock A, clock B, and clock S (scaled). Clock A can be software
selected to be E, E/2, E/4, or E/8. Clock B can be software selected to be E, E/2, E/4,..., E/128.
The scaled clock (clock S) uses clock A as an input and divides it with a reloadable counter. The
rates available are software selectable to be clock A/2, down to clock A /512.
The clock source portion of the block diagram shows the three clock sources and how the scaled
clock is created. Clock A is an input to an 8-bit counter which is then compared to a user
programmable scale value. When they match, this circuit has an output that is divided by two and
the counter is reset.
Each PWM timer channel can be driven by one of two clocks. Refer to Figure 9-6.
PCKA[2:1] — Prescaler for clock A
Determines the frequency of clock A. Refer to Table 9-4.
Bit 3 — Not implemented; always reads zero
PCKB[3:1] — Prescaler for clock B
Determines the frequency of clock B. Refer to Table 9-4.
Table 9-4 Clock A and clock B prescalers
9
PCKA[2:1]
00
Clock A
E
PCKB[3:1]
000
Clock B
E
01
E/2
001
E/2
10
E/4
010
E/4
11
E/8
011
E/8
100
E/16
101
E/32
110
E/64
111
E/128
9-40
TIMING SYSTEM
MC68HC11KW1