MC68HC11KW1 Datasheet, PDF (139/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

OR — Overrun error flag
1 (set) – Overrun detected.
0 (clear) – No overrun.
OR is set if a new character is received before a previously received character is read from SCDR.
Clear the OR flag by reading SCSR1 with OR set and then reading SCDR.
NF — Noise error flag
1 (set) – Noise detected.
0 (clear) – Unanimous decision.
NF is set if the majority sample logic detects anything other than a unanimous decision. Clear NF
by reading SCSR1 with NF set and then reading SCDR.
FE — Framing error
1 (set) – Zero detected.
0 (clear) – Stop bit detected.
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading
7
SCSR1 with FE set and then reading SCDR.
PF — Parity error flag
1 (set) – Incorrect parity detected.
0 (clear) – Parity correct.
PF is set if received data has incorrect parity. Clear PF by reading SCSR1 with PE set and then
reading SCDR.
7.6.5 SCSR2 — SCI status register 2
SCI status 2 (SCSR2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0075 0
0
0
0
0
0
0 RAF 0000 0000
In the SCSR2 only bit 0 is used, to indicate receiver active. The other seven bits always read zero.
Bits [7:1] — Not implemented; always read zero
RAF — Receiver active flag (read only)
1 (set) – A character is being received.
0 (clear) – A character is not being received.
MC68HC11KW1
SERIAL COMMUNICATIONS INTERFACE
7-11