MC68HC11KW1 Datasheet, PDF (75/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

4.4.6
MM1CR, MM2CR – Memory mapping window 1 and 2
control registers
Memory mapping window 1 control
(MM1CR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0058 0 X1A18 X1A17 X1A16 X1A15 X1A14 X1A13 0 0000 0000
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
4
Memory mapping window 2 control
(MM2CR)
$0059
0 X2A18 X2A17 X2A16 X2A15 X2A14 X2A13 0 0000 0000
These two window registers indicate which bank of a window is active. Each contains the value to
be output when the CPU selects addresses within the extended memory window. To change
banks, write the address of the new bank into the appropriate window register.
Bits 7 and 0 — Not implemented; always read zero.
MM1CR — Memory mapping window 1 control register
When a 64K byte CPU address falls within window 1, the value in MM1CR is driven out from the
corresponding expansion address lines to enable the specified bank in the window.
MM2CR — Memory mapping window 2 control register
When a 64K byte CPU address falls within window 2, the value in MM2CR is driven out from the
corresponding expansion address lines to enable the specified bank in the window.
Overlap guidelines:
– On-chip registers, RAM, and EEPROM have higher priority than expansion
windows. If a window overlaps RAM, registers or EEPROM, they appear in
all banks at their CPU address.
– Window 1 has a higher priority than window 2, therefore any overlapped
portion of window 2 is inaccessible.
MC68HC11KW1
OPERATING MODES AND ON-CHIP MEMORY
4-31