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MC68HC11KW1 Datasheet, PDF (97/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit | |||
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5.2.1 Central processing unit
After reset, the CPU fetches the restart vector from the appropriate address during the ï¬rst three
cycles, and begins executing instructions. The stack pointer and other CPU registers are
indeterminate immediately after reset; however, the X and I interrupt mask bits in the condition
code register (CCR) are set to mask any interrupt requests. Also, the S-bit in the CCR is set to
inhibit the STOP mode.
5.2.2 Memory map
After reset, the INIT register is initialized to $00, putting the 768 bytes of RAM at locations
$00A0â$039F, and the control registers at locations $0000â$009F. The INIT2 register puts
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EEPROM at locations $0D80â$0FFF.
5.2.3 Parallel I/O
When a reset occurs in expanded operating modes, port B, C, and F pins used for parallel I/O are
dedicated to the expansion bus. If a reset occurs during a single chip operating mode, all ports are
conï¬gured as general purpose high-impedance inputs.
Note:
Do not confuse pin function with the electrical state of the pin at reset. All
general-purpose I/O pins conï¬gured as inputs at reset are in a high-impedance state.
Port data registers reï¬ect the portâs functional state at reset. The pin function is mode
dependent.
5.2.4 Timer 1
During reset, the Timer 1 system is initialized to a count of $0000. The prescaler bits for Timer 1
are cleared, and all output compare registers are initialized to $FFFF. All input capture registers
are indeterminate after reset. The output compare 1 mask (OC1M) register is cleared so that
successful OC1 compares do not affect any I/O pins. The other four output compares are
conï¬gured so that they do not affect any I/O pins on successful compares. All input capture
edge-detector circuits are conï¬gured for capture disabled operation. The timer overï¬ow interrupt
ï¬ags and all eight timer function interrupt ï¬ags are cleared. All nine timer interrupts are disabled
because their mask bits have been cleared.
The I4/O5 bit in the PACTL register is cleared to conï¬gure the I4/O5 function as OC5; however,
the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not control the PA3 pin.
MC68HC11KW1
RESETS AND INTERRUPTS
5-7
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