MC68HC11KW1 Datasheet, PDF (83/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Table 4-17 One chip select driving another
G1DG
2
G1DPC
G2DP
C
Program CS pin asserted when
address is in:
General 2 CS pin asserted General 1 CS pin asserted
when address is in:
when address is in:
0
0
0
A valid program area
A valid general 2 area
A valid general 1 area
0
0
1 A valid program or general 2 area
Never asserted
A valid general 1 area
0
1
0 A valid program or general 1 area
A valid general 2 area
Never asserted
0
1
1 A valid program or general 1 or 2 area
Never asserted
Never asserted
1
0
0
A valid program area
A valid general 2 or general 1 area
Never asserted
1
0
1 A valid program or general 2 area
Never asserted
A valid general 1 area
4
1
1
0 A valid program or general 1 area
A valid general 2 area
Never asserted
1
1
1 A valid program or general 1 or 2 area
Never asserted
Never asserted
4.5.7 Clock stretching
Each chip select has two bits that enable clock stretching from zero to three cycles. A clock stretch
can be programmed to occur only during accesses to addresses in that chip select's address
range. During the clock stretch period the E clock is held high for additional full periods and the
bus remains in its normal state at the end of the E high time. Internally the clocks keep running so
the integrity of the timers and baud rate generators is maintained.
4.5.7.1 CSCSTR — Chip select clock stretch register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Chip select clock stretch (CSCSTR) $005A IOSA IOSB GP1SA GP1SB GP2SA GP2SB PCSA PCSB 0000 000x
Each of the following pairs of bits determines the clock stretch for one of the four chip selects.
IOSA, IOSB — CSIO stretch select
GP1SA, GP1SB — CSGP1 stretch select
GP2SA, GP2SB — CSGP2 stretch select
PCSA, PCSB — CSPROG stretch select
In normal modes (SMOD = 0), PCSB is set on reset to give a one cycle stretch. In special modes
(SMOD = 1), PCSB is cleared on reset.
Bit [A: B]
00
01
10
11
Clock stretch
Disabled
1 cycle
2 cycles
3 cycles
MC68HC11KW1
OPERATING MODES AND ON-CHIP MEMORY
4-39