MC68HC11KW1 Datasheet, PDF (234/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

effect on I/O 5-7
effect on memory map 5-7
effect on pulse accumulator 5-8
effect on RTI 5-8
effect on SCI 5-8
effect on SPI 5-9
effect on system 5-9
effect on timer 5-7
effects of 5-6
external 5-2
HPRIO — Highest priority I-bit interrupt and misc. reg.
5-10
power-on, POR 5-1
priorities 5-9
processing flow 5-17
RESET pin 5-2
, vectors 5-6 5-12
resetting the COP watchdog 5-3
RFI 2-4
RIE - bit in SCCR2 7-9
ROW - bit in PPROG 4-42
, RTI 9-1 9-31
PACTL — Pulse accumulator control reg. 9-33
rates 9-31
reset 5-8
TFLG2 — Timer interrupt flag reg. 2 9-32
TMSK2 — Timer interrupt mask reg. 2 9-31
RTIF - bit in TFLG2 9-32
RTII - bit in TMSK2 9-31
RTR[1:0] - bits in PACTL 9-33
, RWU - bit in SCCR2 7-4 7-9
S
S-bit in CCR 3-6
SBK - bit in SCCR2 7-9
SBR[12:0] - bits in SCBDH/L 7-6
SCAN - bit in ADCTL 10-7
SCBDH, SCBDL — SCI baud rate control reg. 7-6
SCCR1 — SCI control reg. 1 7-7
SCCR2 — SCI control reg. 2 7-9
SCDRH, SCDRL — SCI data high/low reg. 7-12
SCI 7-1
, baud rate 7-1 7-6
block diagram 7-3
data format 7-2
error detection 7-5
, interrupt source resolution 5-22 7-14
pins 7-1
receive operation 7-2
reset 5-8
SCBDH, SCBDL — SCI baud rate control reg. 7-6
SCCR1 — SCI control reg. 1 7-7
SCCR2 — SCI control reg. 2 7-9
SCDRH, SCDRL — SCI data high/low reg. 7-12
SCSR1 — SCI status reg. 1 7-10
SCSR2 — SCI status reg. 2 7-11
status flags 7-12
transmit operation 7-2
wakeup 7-4
SCK 8-4
SCSR1 — SCI status reg. 1 7-10
SCSR2 — SCI status reg. 2 7-11
security 4-45
mask option 4-45
NOSEC bit 4-46
, sensitivity, of interrupts 2-5 4-16
serial communications interface - see SCI
serial peripheral interface - see SPI
slave select (SS) 8-4
SMOD - bit in HPRIO 4-11
software interrupt (SWI) 5-14
SPCR — Serial peripheral control reg. 8-6
SPDR — SPI data reg. 8-9
SPE - bit in SPCR 8-6
SPI 8-1
block diagram 8-2
, buffering 8-1 8-9
clock phase 8-3
clock polarity 8-7
, clock rate 8-4 8-7
errors 8-5
master mode 8-6
MISO 8-4
MOSI 8-4
OPT2 — System configuration options reg. 2 8-9
pins 8-1
polarity 8-3
reset 5-9
SCK 8-4
signals 8-3
SPCR — Serial peripheral control reg. 8-6
SPDR — SPI data reg. 8-9
SPSR — Serial peripheral status reg. 8-8
SS 8-4
, transfer formats 8-2 8-3
, SPIE - bit in SPCR 8-5 8-6
SPIF - bit in SPSR 8-8
SPR1 and SPR0 - bits in SPCR 8-7
SPR2 - bit in OPT2 8-10
SPSR — Serial peripheral status reg. 8-8
stack pointer (SP) 3-2
stacking operations 3-3
stand-by voltage 2-5
status flags, SCI 7-12
, STOP mode 4-4 5-16
disabling 3-6
SWI 5-14
SYNC - bit in OPT2 7-6
system reset 5-9
T
T2C4 — Timer 2 channel 4 register 9-19
T2FLG — Timer 2 interrupt flag register 9-23
T2MSK — Timer 2 interrupt mask register 9-22
T2OC1—T2OC3 — Timer 2 output compare registers 9-19
T2STP - bit in TCTL4 9-22
INDEX
MC68HC11KW1
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