MC68HC11KW1 Datasheet, PDF (44/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

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Table 3-2 Instruction set (Page 6 of 6)
Mnemonic
SUBA (opr)
Operation
Subtract memory from A
SUBB (opr)
Subtract memory from B
SUBD (opr)
Subtract memory from D
SWI
TAB
TAP
TBA
TEST
TPA
TST (opr)
TSTA
TSTB
TSX
TSY
TXS
TYS
WAI
XGDX
XGDY
Software interrupt
Transfer A to B
Transfer A to CC register
Transfer B to A
Test (only in test modes)
Transfer CC register to A
Test for zero or minus
Test A for zero or minus
Test B for zero or minus
Transfer stack pointer to X
Transfer stack pointer to Y
Transfer X to stack pointer
Transfer Y to stack pointer
Wait for interrupt
Exchange D with X
Exchange D with Y
Description
A–M⇒A
B–M⇒B
D – M:M+1 ⇒ D
see Figure 3-2
A⇒B
A ⇒ CCR
B⇒A
address bus increments
CCR ⇒ A
M–0
A–0
B–0
SP + 1 ⇒ IX
SP + 1 ⇒ IY
IX – 1 ⇒ SP
IY – 1 ⇒ SP
stack registers & WAIT
IX ⇒ D; D ⇒ IX
IY ⇒ D; D ⇒ IY
Addressing
mode
A IMM
A DIR
A EXT
A IND, X
A IND,Y
B IMM
B DIR
B EXT
B IND, X
B IND,Y
IMM
DIR
EXT
IND, X
IND, Y
INH
INH
INH
INH
INH
INH
EXT
IND, X
IND, Y
A INH
B INH
INH
INH
INH
INH
INH
INH
INH
Opcode
80
90
B0
A0
18 A0
C0
D0
F0
E0
18 E0
83
93
B3
A3
18 A3
3F
16
06
17
00
07
7D
6D
18 6D
4D
5D
30
18 30
35
18 35
3E
8F
18 8F
Instruction
Operand
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
—
—
—
—
—
—
hh ll
ff
ff
—
—
—
—
—
—
—
—
—
Cycles
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
14
2
2
2
†
2
6
6
7
2
2
3
4
3
4
‡
3
4
Condition codes
SXH I NZVC
———— ∆ ∆ ∆ ∆
———— ∆ ∆ ∆ ∆
———— ∆ ∆ ∆ ∆
——— 1 ————
———— ∆ ∆ 0 —
∆↓∆∆∆∆∆∆
———— ∆ ∆ 0 —
————————
————————
———— ∆ ∆ 0 0
———— ∆ ∆ 0 0
———— ∆ ∆ 0 0
————————
————————
————————
————————
————————
————————
————————
Operators
⇒ Is transferred to
• Boolean AND
+ Arithmetic addition, except where used as an
inclusive-OR symbol in Boolean formulae
⊕ Exclusive-OR
* Multiply
: Concatenation
– Arithmetic subtraction, or negation symbol
(Twos complement)
Cycles
†
‡
Infinite, or until reset occurs
12 cycles are used, beginning with the opcode
fetch. A wait state is entered, which remains
in effect for an integer number of MPU E clock
cycles (n) until an interrupt is recognised.
Finally, two additional cycles are used to fetch
the appropriate interrupt vector. (14 + n, total).
Operands
dd 8-bit direct address ($0000–$00FF); the high byte is assumed
to be zero
ff 8-bit positive offset ($00 to $FF (0 to 256)) is added to the
contents of the index register
hh High order byte of 16-bit extended address
ii One byte of immediate data
jj High order byte of 16-bit immediate data
kk Low order byte of 16-bit immediate data
ll Low order byte of 16-bit extended address
mm 8-bit mask (set bits to be affected)
rr Signed relative offset ($80 to $7F (–128 to +127));
offset is relative to the address following the offset byte
Condition Codes
— Bit not changed
0 Bit always cleared
1 Bit always set
∆ Bit set or cleared, depending on the operation
↓ Bit can be cleared, but cannot become set
? Not defined
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CENTRAL PROCESSING UNIT
MC68HC11KW1