MC68HC11KW1 Datasheet, PDF (34/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine (BSR)
instruction, the address of the instruction after the JSR or BSR is automatically pushed onto the
stack, less significant byte first. When the subroutine is finished, a return from subroutine (RTS)
instruction is executed. The RTS pulls the previously stacked return address from the stack, and
loads it into the program counter. Execution then continues at this recovered return address.
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When an interrupt is recognized, the current instruction finishes normally, the return address (the
current value in the program counter) is pushed onto the stack, all of the CPU registers are pushed
onto the stack, and execution continues at the address specified by the vector for the interrupt. At
the end of the interrupt service routine, an RTI instruction is executed. The RTI instruction causes
the saved registers to be pulled off the stack in reverse order. Program execution resumes at the
return address.
There are instructions that push and pull the A and B accumulators and the X and Y index
registers. These instructions are often used to preserve program context. For example, pushing
accumulator A onto the stack when entering a subroutine that uses accumulator A, and then
pulling accumulator A off the stack just before leaving the subroutine, ensures that the contents of
a register will be the same after returning from the subroutine as it was before starting the
subroutine.
3.1.5 Program counter (PC)
The program counter, a 16-bit register, contains the address of the next instruction to be executed.
After reset, the program counter is initialized from one of six possible vectors, depending on
operating mode and the cause of reset.
Table 3-1 Reset vector comparison
Normal
Test or Boot
POR or RESET pin
$FFFE, $FFFF
$BFFE, $BFFF
Clock monitor
$FFFC, $FFFD
$BFFE, $BFFF
COP watchdog
$FFFA, $FFFB
$BFFE, $BFFF
3.1.6 Condition code register (CCR)
This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two interrupt masking
bits, (IRQ and XIRQ) and a stop disable bit (S). In the M68HC11 CPU, condition codes are
automatically updated by most instructions. For example, load accumulator A (LDAA) and store
accumulator A (STAA) instructions automatically set or clear the N, Z, and V condition code flags.
Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange instructions do not affect
the condition codes. Refer to Table 3-2, which shows the condition codes that are affected by a
particular instruction.
CENTRAL PROCESSING UNIT
MC68HC11KW1
3-4