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MC68HC11KW1 Datasheet, PDF (218/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit
A.5.4 Non-multiplexed expansion bus timing
A
(VDD = 5.0Vdc ± 5%, VSS = 0Vdc, TA = TL to TH)
Num
Characteristic (1)
4.0 MHz
Symbol
Unit
Min. Max.
Frequency of operation (E clock frequency)
fOP
0
1 E clock period
2 Pulse width, E low (2), (3)
3 Pulse width, E high (2), (3), (4)
tCYC 250
PWEL 105
PWEH 100
4A E clock
4B
9 Address hold time (3)
11 Address delay time (3)
12 Address valid to E rise time (3)
rise time tR
—
fall time tF
—
tAH
21
tAD
—
tAV
34
17 Read data set-up time
tDSR
20
18 Read data hold time
tDHR
0
19 Write data delay time
21 Write data hold time (3)
29 MPU address access time (3), (4)
39 Write data set-up time (3), (4)
tDDW
—
tDHW 31
tACCA 144
tDSW 60
50 E valid chip select delay time
51 E valid chip select access time (4)
tECSD —
tECSA 40
52 Chip select hold time
tCH
0
54 Address valid chip select delay time
55 Address valid chip select access time (4)
tACSD —
tACSA 113
56 Address valid to chip select time
tAVCS 10
57 Address valid to data three-state time
tAVDZ —
4.0 MHz
— ns
— ns
— ns
20
15
ns
— ns
71 ns
— ns
— ns
— ns
40 ns
— ns
— ns
— ns
45 ns
— ns
25 ns
103 ns
— ns
— ns
10 ns
(1) All timing is given with respect to 20% and 70% of VDD, unless otherwise noted.
(2) Input clock duty cycles other than 50% will affect the bus performance.
(3) For fOP ≤ 2MHz the following formulae may be used to calculate parameter values:
PWEL = tCYC/2 – 20ns
PWEH = tCYC/2 – 25ns
tAH = tCYC/8 – 10ns
tAD = tCYC/8 + 40ns
tAV = PWEL – tAD
tDHW = tCYC/8
tACCA = tCYC – tF – tDSR – tAD
tDSW = PWEH – tDDW
tECSA = PWEH – tECSD – tDSR
tACSA = tCYC – tF – tDSR – tACSD
(4) Indicates a parameter affected by clock stretching. Add n(tCYC) to the parameter value,
where n = 1, 2 or 3, depending on the valued written to the CSCSTR register.
A-14
ELECTRICAL SPECIFICATIONS
MC68HC11KW1