MC68HC11KW1 Datasheet, PDF (230/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

CON34 - bit in PWCLK 9-38
concatenation, of PWM 9-38
CONFIG — System configuration reg. 4-12
programming 4-44
configuration 4-12
CONV8 - bit in ADCTL 10-7
, COP 9-3 9-33
CONFIG — Configuration control reg. 5-5
COPRST — Arm/reset COP timer circuitry reg. 5-3
enable 5-6
OPTION — System configuration options reg. 1 5-4
, rates 5-2 5-5
, , reset 5-2 5-3 5-8
timeout 5-2
COPRST — Arm/reset COP timer circuitry reg. 5-3
corruption
of A/D 6-6
of memory 2-2
, , CPHA - bit in SPCR 8-3 8-4 8-7
CPOL - bit in SPCR 8-7
CPU
accumulators (A, B and D) 3-2
architecture 3-1
CCR — condition code reg. 3-4
index registers (IX, IY) 3-2
program counter (PC) 3-4
programming model 3-1
registers 3-1
reset 5-7
CR[1:0] - bits in OPTION 5-5
CSCSTR — Chip select clock stretch register 4-39
CSTL — Chip select control register 4-34
CWOM - bit in OPT2 6-14
D
data format, SCI 7-2
data types 3-6
DDA[7:0] - bits in DDRA 6-2
DDB[7:0] - bits in DDRB 6-3
DDC[7:0] - bits in DDRC 6-4
DDD[5:0] - bits in DDRD 6-5
DDF[7:0] - bits in DDRF 6-7
DDG[7:0] - bits in DDRG 6-9
DDH[7:0] - bits in DDRH 6-10
DDJ[7:0] - bits in DDRJ 6-11
DDK[7:0] - bits in DDRK 6-12
DDRA — Data direction reg. for port A 6-2
DDRB — Data direction reg. for port B 6-3
DDRC — Data direction reg. for port C 6-4
DDRD — Data direction reg. for port D 6-5
DDRF — Data direction reg. for port F 6-7
DDRG — Data direction reg. for port G 6-9
DDRH — Data direction reg. for port H 6-10
DDRJ — Data direction reg. for port J 6-11
DDRK — Data direction reg. for port K 6-12
development tools C-1
DIR - direct addressing mode 3-7
DISCP - bit in PWEN 9-42
DLY - bit in OPTION 4-16
duty cycle, PWM 9-44
DWOM - bit in SPCR 8-6
E
E clock pin 2-4
ECEB, ECEA - bits in TCTL4 9-21
ECEB, ECEA - bits in TCTL6 9-28
EDGB, EDGA - bits in TCTL4 9-21
EDGB, EDGA - bits in TCTL6 9-27
EDGxA and EDGxB - bits in TCTL2 9-6
EELAT - bit in PPROG 4-42
EEON - bit in CONFIG 4-13
EEPGM - bit in PPROG 4-42
– EEPROM 4-41 4-44
erased state ($FF) 4-41
– erasing 4-43 4-44
PPROG — EEPROM programming control reg. 4-41
security 4-45
EEx - bits in INIT2 4-15
ERASE - bit in PPROG 4-42
erased state
EEPROM ($FF) 4-41
error detection, SCI 7-5
ESD protection A-1
EVEN - bit in PPROG 4-41
event counter - see pulse accumulator
EVS — Evaluation system C-1
, expansion address lines 4-23 4-24
EXTAL pin 2-3
F
F23FRC — Compare force reg. for timers 2 and 3 9-18
FCME - bit in OPTION 5-5
FE - bit in SCSR1 7-11
FOC[1:5] - bits in CFORC 9-10
FPPUE - bit in PPAR 6-13
free-running counter 9-1
FT3Cx, FT2Cx - bits in F23FRC 9-19
G
G1A[18:11] - bits in GPCS1A 4-35
G1AV - bit in GPCS1C 4-36
G1DG2 - bit in GPCS1C 4-36
G1DPC - bit in GPCS1C 4-36
G1POL - bit in GPCS1C 4-36
G1SZA—G1SZD - bits in GPCS1C 4-36
G2A[18:11] - bits in GPCS2A 4-37
G2AV - bit in GPCS2C 4-38
G2DPC - bit in GPCS2C 4-37
G2POL - bit in GPCS2C 4-38
G2SZA—G2SZD - bits in GPCS2C 4-38
GCSPR - bit in CSCTL 4-34
INDEX
MC68HC11KW1
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