MC68HC11KW1 Datasheet, PDF (140/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

7.6.6 SCDRH, SCDRL — SCI data high/low registers
SCI data high (SCDRH)
SCI data low (SCDRL)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0076 R8 T8 0
0
0
0
0
0 undefined
$0077 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 undefined
SCDRH/SCDRL is a parallel register that performs two functions. It is the receive data register
when it is read, and the transmit data register when it is written. Reads access the receive data
buffer and writes access the transmit data buffer. Data received or transmitted is double buffered.
If the SCI is being used with 7 or 8-bit data, only SCDRL needs to be accessed. Note that if 9-bit
data format is used, the upper register should be written first to ensure that it is transferred to the
transmitter shift register with the lower register.
R8 — Receiver bit 8
Ninth serial data bit received when SCI is configured for a nine data bit operation
7
T8 — Transmitter bit 8
Ninth serial data bit transmitted when SCI is configured for a nine data bit operation
Bits [5:0] — Not implemented; always read zero
R/T[7:0] — Receiver/transmitter data bits [7:0]
SCI data is double buffered in both directions.
7.7
Status flags and interrupts
The SCI transmitter has two status flags. These status flags can be read by software (polled) to
tell when certain conditions exist. Alternatively, a local interrupt enable bit can be set to enable
each of these status conditions to generate interrupt requests. Status flags are automatically set
by hardware logic conditions, but must be cleared by software. This provides an interlock
mechanism that enables logic to know when software has noticed the status indication. The
software clearing sequence for these flags is automatic — functions that are normally performed
in response to the status flags also satisfy the conditions of the clearing sequence.
TDRE and TC flags are normally set when the transmitter is first enabled (TE set to one). The
TDRE flag indicates there is room in the transmit queue to store another data character in the
transmit data register. The TIE bit is the local interrupt mask for TDRE. When TIE is zero, TDRE
must be polled. When TIE and TDRE are one, an interrupt is requested.
7-12
SERIAL COMMUNICATIONS INTERFACE
MC68HC11KW1