MC68HC11KW1 Datasheet, PDF (201/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

10.4.1 4-channel single scan
A group of four channels is selected by the CD and CC bits in the ADCTL register (see Table 10-1).
The first result is stored in the ADR5 result register, the second in ADR6, the third in ADR7 and
the fourth in the ADR8 register. After the fourth conversion is complete, all conversion activity is
halted until a new conversion command is written to the ADCTL control register.
10.4.2 4-channel continuous scan
Conversions continue to be performed on the selected group of channels with the fifth conversion
being stored in the ADR5 register (replacing the earlier conversion result for the first channel in
the group), the sixth conversion overwrites ADR6, the seventh overwrites ADR7, and so on,
continuously. Using this second variation the data in any result register is, at most, four conversion
times old.
10.4.3 8-channel single scan
When CONV8 is set and MULT is set, then a group of eight channels is converted. The group is
selected by the CD bit. Each of the channels is converted and the result is placed in a separate
result register. Port E pin 0 uses result register ADR1, Port E pin 1 uses result register ADR2 and
so on. Each channel is converted once, then all conversion activity is halted until a new conversion
command is written to the ADCTL control register.
10.4.4 8-channel continuous scan
Conversions continue to be performed on the eight channels with the ninth conversion being
stored in the ADR1 register (replacing the earlier conversion result for the first channel in the
group), the tenth conversion overwrites ADR2, the eleventh overwrites ADR3, and so on,
continuously. Using this second variation the data in any result register is, at most, eight
conversion times old.
10
10.5
Power-up and clock select
A/D power up is controlled by the ADPU bit in the OPTION register. When ADPU is cleared, power
to the A/D system is removed. When ADPU is set, the A/D system is enabled. A delay of 100
microseconds is required after turning on the A/D converter, to allow the analog bias voltages to
stabilize.
Clock select is controlled by the CSEL bit in the OPTION register. When CSEL is cleared, the A/D
system uses the system E-clock. When CSEL is set, the A/D system uses an internal R-C clock
MC68HC11KW1
ANALOG-TO-DIGITAL CONVERTER
10-5