MC68HC11KW1 Datasheet, PDF (121/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

6.7.2 DDRG — Data direction register for port G
Data direction G (DDRG)
Address bit 7
$007F 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
0 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0000 0000
Bits [7, 6] — Not implemented; always read zero
DDG[5:0] — Data direction for port G
1 (set) – The corresponding pin is configured as an output.
0 (clear) – The corresponding pin is configured as an input.
6.7.3 PGAR — Port G assignment register
6
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port G assignment (PGAR)
$002D 0
0 PGAR5 PAGR4 PGAR3 PGAR2 PGAR1 PGAR0 0000 0000
PGAR selects which port G pins are used for I/O or memory expansion address lines, defining
which extended address lines are used. Selecting an address on one of these pins causes a port
G pin to be lost. For this reason, select only those address lines that are needed by the expansion
logic. This allows unused lines to serve as general-purpose I/O. For more information, refer to
Section 4.4.
Bits [7:6] — Not implemented; always read zero
PGAR[5:0] — Port G pin assignment
1 (set) – Corresponding port G pin is expansion address line (XA[18:13]).
0 (clear) – Corresponding port G pin is general-purpose I/O.
MC68HC11KW1
PARALLEL INPUT/OUTPUT
6-9