MC68HC11KW1 Datasheet, PDF (170/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.2.1 Output compare
There are three dedicated output compare registers associated with Timer 2 (T20C[3:1]). In
addition, a fourth register (T2C4) is used either for a fourth output compare function or for an input
capture function, depending on the state of the I1/O4 bit in the TCTL4 register.
The output compare function operates in a similar fashion to that on Timer 1; a value written to an
output compare register is compared to the free running counter value during each clock cycle. If
a match is found, the appropriate output compare flag is set in the interrupt flag register (T2FLG).
An interrupt is then generated if that particular interrupt is enabled in the interrupt mask register
(T2MSK). Unlike Timer 1, which has separate interrupt requests for each interrupt, Timer 2 output
compare interrupts 1,2 and 3 are associated with a single interrupt sequence. This means that flag
polling is required if more than one interrupt is enabled. Refer to Figure 9-3.
In addition to an interrupt, a successful output compare can trigger a specified action at the
associated output port pins PJ [7:4]. The type of action taken is defined by bits in timer control
register TCTL3. This action may be forced by setting the appropriate bit in the F23FRC register
(see Section 9.2.3).
9.2.2 Input capture
When configured as an input capture register, the 16-bit T2C4 register is used to latch the value
of the counter when a selected transition at pin PJ7 is detected. The type of transition which
triggers the capture is defined by the EDGA and EDGB bits in the TCTL4 register.
9 _9.2.3
F23FRC — Compare force register for Timers 2 and 3.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Compare force for Timers 2 and 3 (F23FRC) $0031 FT3C1 FT3C2 FT3C3 FT3C4 FT2C1 FT2C3 FT2C3 FT2C4 0000 0000
The F23FRC register allows forced early compares for Timers 2 and 3. Bits [7:4] correspond to
the four output compares of Timer 3, and bits [3:0] correspond to those of Timer 2. These bits are
set for each output compare that is to be forced. The action taken as a result of a forced compare
is the same as if there were a match between the OCx register and the free-running counter,
except that the corresponding interrupt status flag bits are not set. The forced channels trigger
their programmed pin actions to occur at the next timer count transition after the write to F23FRC.
The F23FRC bits should not normally be used on an output compare function that is programmed
to toggle its output on a successful compare, because a normal compare occurring immediately
before or after the force would produce a double toggle. This may be undesirable if it happens
quickly, since the resulting output pulse would be very short.
9-18
TIMING SYSTEM
MC68HC11KW1