MC68HC11KW1 Datasheet, PDF (92/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

5.1.2 External reset (RESET)
The CPU distinguishes between internal and external reset conditions by sensing whether the
reset pin rises to a logic one in less than four E clock cycles after an internal device releases reset.
When a reset condition is sensed, the RESET pin is driven low by an internal device for eight E
clock cycles, then released. Four E clock cycles later it is sampled. If the pin is still held low, the
CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor. It is not advisable to connect an
external resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices
because the circuit charge time constant can cause the device to misinterpret the type of reset
that occurred. To guarantee recognition of an external reset, the RESET pin should be held low
5
for at least 16 clock cycles.
5.1.3 COP reset
The MCU includes a COP system to help protect against software failures. When the COP is enabled,
the software is responsible for keeping a free-running watchdog timer from timing out. When the
software is no longer being executed in the intended sequence, a system reset is initiated.
The state of the NOCOP bit in the CONFIG register determines whether the COP system is
enabled or disabled. To change the enable status of the COP system, change the contents of the
CONFIG register and then perform a system reset. In the special test and bootstrap operating
modes, the COP system is initially inhibited by the disable resets (DISR) control bit in the TEST1
register. The DISR bit can subsequently be written to zero to enable COP resets.
The COP timer rate control bits, CR[1:0], in the OPTION register determine the COP timeout
period. The system E clock is divided by 2¹⁵ and then further scaled by the factor shown in
Table 5-1. After reset, bits CR[1:0] are zero, which selects the shortest timeout period. In normal
operating modes, these bits can only be written once, within 64 bus cycles after reset.
Table 5-1 COP timer rate select
CR[1:0] Divide E/2¹⁵ by
00
1
01
4
10
16
11
64
E=
EXTAL = 16 MHz: timeout ⁽¹⁾
8.192 ms
32.768 ms
131.072 ms
524.288 ms
4 MHz
(1) The timeout period has a tolerance of –0/+one cycle of the E/2¹⁵
clock due to the asynchronous implementation of the COP circuitry.
For example, with E = 4 MHz, the uncertainty is –0/+8.192 ms. See
also the M68HC11 Reference Manual, (M68HC11RM/AD).
RESETS AND INTERRUPTS
MC68HC11KW1
5-2