MC68HC11KW1 Datasheet, PDF (95/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

This control bit can be read or written at any time and controls whether or not the internal clock
monitor circuit triggers a reset sequence when the system clock is slow or absent. When it is clear,
the clock monitor circuit is disabled, and when it is set, the clock monitor circuit is enabled. Reset
clears the CME bit.
In order to use both STOP and clock monitor, the CME bit should be cleared before executing
STOP, then set again after recovering from STOP.
FCME — Force clock monitor enable
1 (set) – Clock monitor enabled; cannot be disabled until next reset.
0 (clear) – Clock monitor follows the state of the CME bit.
When FCME is set, slow or stopped clocks will cause a clock failure reset sequence. To utilize
5
STOP mode, FCME should always be cleared.
CR[1:0] — COP timer rate select bits
The internal E clock is first divided by 2¹⁵ before it enters the COP watchdog system. These control
bits determine a scaling factor for the watchdog timer period. See Table 5-1.
5.1.6 CONFIG — Configuration control register
Configuration control (CONFIG)
Address bit 7
$003F 1
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
1
CLKX
PAREN
NOSEC
NOCO
P
1
EEON 11xx 1x1x
Included in CONFIG are bits which control the presence of EEPROM in the memory map and
enable the COP watchdog system.
CONFIG is made up of EEPROM cells and static working latches. The operation of the MCU is
controlled directly by these latches and not the EEPROM byte. When programming the CONFIG
register, the EEPROM byte is accessed. When the CONFIG register is read, the static latches
are accessed.
These bits can be read at any time. The value read is the one latched into the register from the
EEPROM cells during the last reset sequence. A new value programmed into this register is not
readable until after a subsequent reset sequence.
Bits in CONFIG can be written at any time if SMOD = 1 (bootstrap or special test mode). If
SMOD = 0 (single chip or expanded mode), these bits can only be written using the EEPROM
programming sequence, and none of the bits are readable or active until latched via the next reset.
Bits [7, 6, 1] — Not implemented; always read one.
MC68HC11KW1
RESETS AND INTERRUPTS
5-5