MC68HC11KW1 Datasheet, PDF (189/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

PAII and PAIF — Pulse accumulator input edge interrupt enable and flag
The PAIF status bit is automatically set each time a selected edge is detected at the PA7/PAI/OC1
pin. To clear this status bit, write to the TFLG2 register with a one in the corresponding data bit
position (bit 4). The PAII control bit allows configuring the pulse accumulator input edge detect for
polled or interrupt-driven operation but does not affect setting or clearing the PAIF bit. When PAII
is zero, pulse accumulator input interrupts are inhibited, and the system operates in a polled mode.
In this mode, the PAIF bit must be polled by user software to determine when an edge has
occurred. When the PAII control bit is set, a hardware interrupt request is generated each time
PAIF is set. Before leaving the interrupt service routine, software must clear PAIF by writing to the
TFLG register.
9.7
Pulse-width modulation (PWM) timer
The PWM timer subsystem provides up to four 8-bit pulse-width modulated waveforms on the port
H pins. Channel pairs can be concatenated to create 16-bit PWM outputs. Three clock sources
(A, B, and S) and a flexible clock select scheme give the PWM a wide range of frequencies.
Pin Alternative function
PH0
PW1
PH1
PW2
PH2
PW3
PH3
PW4
9
Four control registers configure the PWM outputs — PWCLK, PWPOL, PWSCAL, and PWEN.
The PWCLK register selects the prescale value for the PWM clock sources and enables the 16-bit
PWM functions. The PWPOL register determines each channel’s polarity and selects the clock
source for each channel. The PWSCAL register derives a user-scaled clock based on the A clock
source, and the PWEN register enables the PWM channels.
Each channel also has a separate 8-bit counter, period register, and duty cycle register. The period
and duty cycle registers are double buffered so that if they are changed while the channel is
enabled, the change does not take effect until the counter rolls over or the channel is disabled. A
new period or duty cycle can be forced into effect immediately by writing to the period or duty cycle
register and then writing to the counter.
With PWMs configured for 8-bit mode and E equal to 4MHz, PWM signals can be produced from
40 kHz (1% duty cycle resolution) to less than 10 cycles per second (approximately 0.4% duty
cycle resolution). By configuring the PWMs for 16-bit mode with E equal to 4MHz, PWM periods
greater than one minute are possible.
In 16-bit mode, duty cycle resolution of up to 15 parts per million can be achieved (at a PWM
frequency of 60Hz). In the same system, a PWM frequency of 1kHz corresponds to a duty cycle
resolution of 0.025%.
MC68HC11KW1
TIMING SYSTEM
9-37