MC68HC11KW1 Datasheet, PDF (7/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

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4.3.2 Initialization ......................................................................................................4-12
4.3.2.1
CONFIG — System configuration register .................................................4-12
4.3.2.2
INIT — RAM and I/O mapping register ......................................................4-13
4.3.2.3
INIT2 — EEPROM mapping register..........................................................4-15
4.3.2.4
OPTION — System configuration options register 1..................................4-15
4.3.2.5
OPT2 — System configuration options register 2 ......................................4-17
4.3.2.6
BPROT — Block protect register................................................................4-18
4.3.2.7
TMSK2 — Timer interrupt mask register 2 .................................................4-20
4.3.2.8
TCTL4 and TCTL6 — Timer 2 and 3 control registers ...............................4-21
4.4 Memory expansion ................................................................................................4-22
4.4.1 Memory expansion logic ..................................................................................4-22
4.4.2 Extended addressing .......................................................................................4-23
4.4.3 Memory expansion examples ..........................................................................4-24
4.4.4 MMSIZ — Memory mapping window size register...........................................4-29
4.4.5 MMWBR – Memory mapping window base register ........................................4-30
4.4.6 MM1CR, MM2CR – Memory mapping window 1 and 2 control registers ........4-31
4.4.7 PGAR — Port G assignment register ..............................................................4-32
4.5 Chip selects ...........................................................................................................4-32
4.5.1 Chip select priorities.........................................................................................4-33
4.5.2 Program chip select .........................................................................................4-33
4.5.3 I/O chip select ..................................................................................................4-33
4.5.4 CSCTL — Chip select control register .............................................................4-34
4.5.5 General-purpose chip selects ..........................................................................4-35
4.5.5.1
GPCS1A — General-purpose chip select 1 address register ....................4-35
4.5.5.2
GPCS1C — General-purpose chip select 1 control register ......................4-36
4.5.5.3
GPCS2A — General-purpose chip select 2 address register ....................4-37
4.5.5.4
GPCS2C — General-purpose chip select 2 control register ......................4-37
4.5.6 One chip select driving another .......................................................................4-38
4.5.7 Clock stretching ...............................................................................................4-39
4.5.7.1
CSCSTR — Chip select clock stretch register ...........................................4-39
4.6 EEPROM and CONFIG register ............................................................................4-41
4.6.1 EEPROM .........................................................................................................4-41
4.6.1.1
PPROG — EEPROM programming control register ..................................4-41
4.6.1.2
EEPROM bulk erase ..................................................................................4-43
4.6.1.3
EEPROM row erase ...................................................................................4-43
4.6.1.4
EEPROM byte erase ..................................................................................4-44
4.6.2 CONFIG register programming ........................................................................4-44
4.6.3 RAM and EEPROM security ............................................................................4-45
5
RESETS AND INTERRUPTS
5.1 Resets ...................................................................................................................5-1
5.1.1 Power-on reset .................................................................................................5-1
5.1.2 External reset (RESET) ...................................................................................5-2
MC68HC11KW1
TABLE OF CONTENTS
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