MC68HC11KW1 Datasheet, PDF (67/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

4.4.2 Extended addressing
Memory expansion is achieved by manipulating the CPU address lines such that, even though the
CPU cannot distinguish more than 64K bytes of physical memory, up to 1M byte can be accessed
through a paged memory scheme. Additional address lines XA[18:13] are provided as alternative
functions of port G pins. Bits in the port G assignment register (PGAR) define which port G pins are to
be used for memory expansion address lines and which are to be used for general-purpose I/O.
In order to access expanded memory, the user must first allocate a range of the 64K byte address
space to be used for the window(s) through which external, expanded memory is viewed by the
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CPU. The size and placement of the window(s) depend on values written to the MMSIZ and
MMWBR registers, respectively. Which bank or page of the expanded memory that is present in
the window(s) at a given time is dependent on values written to the MM1CR and MM2CR
registers.
Up to two windows can be designated and each can be programmed to 0K (disabled), 8K, 16K,
or 32K bytes. The base address for each window must be an integer multiple of the window size,
with the exception of the 32K byte window, for which the base address can be at $0000, $4000,
or $8000.
If the windows are defined in such a way that they overlap, bank window 1 has priority and the part
of window 2 that is not overlapped by bank window 1 remains active. If a window is defined such
that it overlaps any internal registers, RAM, or EEPROM, then the portion of the registers, RAM,
or EEPROM that is overlapped is repeated in all banks associated with that window.
Coming out of reset, the reset vector is fetched from external memory. Since the memory
expansion lines are disabled coming out of reset and can be internally pulled to logic level one,
any external system that uses these expansion address lines sees them as all ones. In this case,
the reset vector is fetched from $7FFFE–$7FFFF. Systems using external but not expanded
memory still fetch the reset vector from $FFFE–$FFFF. This is the reset vector's normal position
at the top of the M68HC11 CPU's conventional 64K byte address space.
Expanded memory is addressed by using a combination of the CPU's normal address lines
ADDR[15:0] and the expansion address lines XA[18:13]. Window size and the number of banks
associated with the window determine exactly which address lines are used. The additional
address lines (XA[18:13]) determine which bank is present in a window at a given time. The lower
three expansion address lines (XA[15:13]) are used only when needed by the CPU and replace
the CPU's equivalent address lines (ADDR[15:13]). Table 4-9 shows which address lines are used
for various configurations of expanded memory.
A special case exists when the bank size is 32K bytes and the window base address is $4000.
Normally, when the bank size is 32K bytes and the bank address is $0000 or $8000, CPU address
lines ADDR[14:0] select individual bytes within the 32K byte space and the ADDR[14:0] pins are
connected to address lines (A[14:0]) of the memory device. When the base address is $4000, the CPU
address signal ADDR14 must be inverted to allow 32K bytes of contiguous memory. The
MC68HC11KW1 CPU drives the inverted CPU ADDR14 signal onto the XA14 pin when the window
is active. In this case, the XA14 signal must be connected to the address line 14 of the memory device.
When the window is not active, the XA14 pin is driven with the non-inverted CPU ADDR14 signal.
MC68HC11KW1
OPERATING MODES AND ON-CHIP MEMORY
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