MC68HC11KW1 Datasheet, PDF (202/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

source, nominally 1.5 MHz, in which case the R-C internal clock should be selected. A delay of 10
milliseconds is required, after changing CSEL from zero to one, to allow the R-C oscillator to start
and internal bias voltages to settle. If the E-clock frequency drops below 750kHz, then the internal
R-C oscillator must be used.
When the A/D system is operating with the MCU E-clock, all switching and comparator operations
are synchronized with the MCU clock. This allows the comparator results to be sampled at quiet
clock times to minimise the effect of internal switching noise. As the internal R-C oscillator is
asynchronous with respect to the MCU clock, internal switching noise is more likely to affect the
overall accuracy of the A/D results, when using this oscillator, than when using the E-clock.
10.6
Operation in STOP and WAIT modes
If a conversion sequence is still in process when the MC68HC11KW1 enters the STOP or WAIT
mode, the conversion of the current channel is suspended. When the MCU resumes normal
operation, that channel is re-sampled and the conversion sequence resumes. As the MCU exits
the WAIT mode, the A/D circuits are stable and valid results can be obtained on the first
conversion. However, in STOP mode the comparator, charge pump and R-C oscillator are turned
off. If the MC68HC11KW1 exits the STOP mode with a delay (as is normal), there will
automatically be enough time for these circuits to stabilize before the first conversion. If the
MC68HC11KW1 exits the STOP mode with no delay (DLY bit in OPTION register equal to zero)
and a stable external clock supplied, the user must allow about 100 microseconds for the A/D
circuitry to stabilize and to avoid invalid results.
10.7
10
10.7.1
Registers
ADCTL — A/D control and status register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
A/D control & status register (ADCTL) $0030 CCF CONV8 SCAN MULT CD CC CB CA undefined
This register can be read and written at any time. Note that a write to this register will always clear
the CCF bit.
CCF — Conversions complete flag
This flag bit is set automatically after an A/D conversion cycle (four or eight conversions, depending on
which conversion mode is selected). If a continuous scan mode is selected, the CCF flag will become
set after the first time all four (or eight) registers have been updated, and it will remain set until the
10-6
ANALOG-TO-DIGITAL CONVERTER
MC68HC11KW1