MC68HC11KW1 Datasheet, PDF (105/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

5.4.5 Maskable interrupts
The maskable interrupt structure of the MCU can be extended to include additional external
interrupt sources through the IRQ pin. The default configuration of this pin is a low-level sensitive
wired-OR network. When an event triggers an interrupt, a software accessible interrupt flag is set.
When enabled, this flag causes a constant request for interrupt service. After the flag is cleared,
the service request is released.
5.4.6 Reset and interrupt processing
The following flow diagrams illustrate the reset and interrupt process. Figure 5-1 and Figure 5-2
illustrate how the CPU begins from a reset and how interrupt detection relates to normal opcode
5
fetches. Figure 5-3 to Figure 5-4 provide an expanded version of a block in Figure 5-1 and illustrate
interrupt priorities. Figure 5-6 shows the resolution of interrupt sources within the SCI subsystem.
5.5
Low power operation
Both STOP and WAIT suspend CPU operation until a reset or interrupt occurs. The WAIT condition
suspends processing and reduces power consumption to an intermediate level. The STOP
condition turns off all on-chip clocks and reduces power consumption to an absolute minimum
while retaining the contents of all bytes of the RAM.
5.5.1 WAIT
The WAI opcode places the MCU in the WAIT condition, during which the CPU registers are
stacked and CPU processing is suspended until a qualified interrupt is detected. The interrupt can
be an external IRQ, an XIRQ, or any of the internally generated interrupts, such as the timer or
serial interrupts. The on-chip crystal oscillator remains active throughout the WAIT stand-by
period.
The reduction of power in the WAIT condition depends on how many internal clock signals driving
on-chip peripheral functions can be shut down. The CPU is always shut down during WAIT. While
in the wait state, the address/data bus repeatedly runs read cycles to the address where the CCR
contents were stacked. The MCU leaves the wait state when it senses any interrupt that has not
been masked.
The free-running Timer 1 system is stopped only if the I-bit is set and the COP system is disabled
by NOCOP being set. Timers 2 and 3 can be stopped under the control of bits in the TCTL4 and
TCTL6 registers, respectively. Several other systems can also be in a reduced power consumption
state depending on the state of software-controlled configuration control bits. Power consumption
by the analog-to-digital (A/D) converter is not affected significantly by the WAIT condition.
MC68HC11KW1
RESETS AND INTERRUPTS
5-15