MC68HC11KW1 Datasheet, PDF (76/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

4.4.7 PGAR — Port G assignment register
Port G assignment (PGAR)
Address bit 7
$002D 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
0 PGAR5 PAGR4 PGAR3 PGAR2 PGAR1 PGAR0 0000 0000
PGAR selects which pins are used for I/O or memory expansion address lines, defining which
extended address lines are used. The memory expansion address lines are shared with port G
4
I/O pins. Selecting an address on one of these pins causes a port G pin to be lost. Therefore, to
allow unused lines to serve as general-purpose I/O, select only those address lines that are
needed by the expansion logic. If neither bank uses a particular expansion address bit, the
corresponding pin is available for general-purpose I/O. If an address line is not required, clear the
appropriate bit in PGAR. (A special case exists for the address lines that overlap the CPU address
lines XA[15:13]. If these lines are selected as address lines in PGAR, but are not used in either
window, the corresponding CPU address line is output on the appropriate port G pin.)
Bits [7:6] — Not implemented; always read zero.
PGAR[5:0] — Port G pin assignment
1 (set) – Corresponding port G pin is expansion address line (XA[18:13]).
0 (clear) – Corresponding port G pin is general-purpose I/O.
4.5
Chip selects
The function of the chip selects is to minimize the amount of external glue logic needed to interface
the MCU to external devices. Such factors as polarity, address block size, and clock stretching can
be controlled using the chip-select registers.
When enabled, a chip select signal is asserted whenever the CPU makes an access to a
designated range of addresses. Bus control signals and chip select signals are synchronous with
the external E clock signal. Refer to the section on expansion bus timing (Section A.5.4) in the
electrical specifications chapter. The length of the external E clock cycle to which the external
device is synchronized can be stretched to accommodate devices that are slower than the MCU.
There are six chip select control registers. Chip select functions are enabled by control bits in the
CSCTL register. When an MCU pin is not used for chip select functions, it can be used for
general-purpose I/O.
The MC68HC11KW1 has four software configured chip selects that are enabled in expanded
modes. The chip select for I/O (CSIO) is used for I/O expansion. The program chip select
(CSPROG) is used with an external memory that contains the reset vectors and program. The two
general-purpose chip selects, CSGP1 and CSGP2, are used to enable external devices. These
external devices can be in the 64K byte memory space or in the expanded memory space.
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OPERATING MODES AND ON-CHIP MEMORY
MC68HC11KW1