MC68HC11KW1 Datasheet, PDF (150/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

8.5.2 SPSR — SPI status register
SPI status (SPSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0029 SPIF WCOL 0 MODF 0
0
0
0 0000 0000
This register can be read at any time, but writing to it has no effect.
SPIF — SPI interrupt complete flag
1 (set) – Data transfer to external device has been completed.
0 (clear) – No valid completion of data transfer.
SPIF is set upon completion of data transfer between the processor and the external device. If
SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. To clear the SPIF bit,
read the SPSR with SPIF set, then access the SPDR. Unless SPSR is read (with SPIF set) first,
attempts to write SPDR are inhibited.
WCOL — Write collision
1 (set) – Write collision.
0 (clear) – No write collision.
8
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an
access of SPDR. Refer to Section 8.3.4 and Section 8.4.
MODF — Mode fault
1 (set) – Mode fault.
0 (clear) – No mode fault.
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to
Section 8.3.4 and Section 8.4.
Bits [5, 3:0] — Not implemented; always read zero.
SERIAL PERIPHERAL INTERFACE
MC68HC11KW1
8-8