MC68HC11KW1 Datasheet, PDF (165/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.1.3.8 TFLG1 — Timer interrupt flag register 1
Timer interrupt flag 1 (TFLG1)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0023 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F 0000 0000
Bits in this register indicate when timer system events have occurred. Coupled with the bits of
TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a polled or interrupt
driven system. Clear flags by writing a one to the corresponding bit position(s).
Note:
Bits in TFLG1 correspond bit for bit with flag bits in TMSK1. Ones in TMSK1 enable the
corresponding interrupt sources.
OC1F–OC4F — Output compare x flag
1 (set) – Counter has reached the preset output compare x value.
0 (clear) – Counter has not reached the preset output compare x value.
These flags are set each time the counter matches the corresponding output compare x values.
I4/O5F — Input capture 4/output compare 5 flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
IC1F–IC3F — Input capture x flag
1 (set) – Selected edge has been detected on corresponding port pin.
9
0 (clear) – Selected edge has not been detected on corresponding port pin.
These flags are set each time a selected active edge is detected on the ICx input line
MC68HC11KW1
TIMING SYSTEM
9-13