MC68HC11KW1 Datasheet, PDF (209/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

A.5
Control timing
(V_DD = 5.0V ± 5%, V_SS = 0Vdc, T_A = T_L to T_H unless otherwise noted)
Characteristic ⁽¹⁾
4.0 MHz
Symbol
Unit
Min. Max.
Frequency of operation
f_OP
0
4.0 MHz
E clock period
t_CYC
250 — ns
Crystal frequency
f_XTAL
— 16.0 MHz
External oscillator frequency
4f_OP
0 16.0 MHz
Processor control setup time
Reset input pulse width ⁽²⁾
(t_PCSU = 1/4 t_CYC + 50 ns) t_PCSU
112
P
W
(3)
RSTL
16
P
W
(4)
RSTL
1
– ns
—
—
t_CYC
Mode programming set-up time
t_MPS
2
— t_CYC
Mode programming hold time
t_MPH
10
— ns
Interrupt pulse width (IRQ edge sensitive mode)
Interrupt pulse period⁽⁵⁾
PW_IRQ 270
—
ns
t_ILIH
Note 5 — t_CYC
WAIT recovery start-up time
t_WRS
—
4
t_CYC
Timer pulse width, input capture pulse accumulator input
PW_TIM = t_CYC + 20 ns PW_TIM 270
—
ns
(1) All timing is given with respect to 20% and 70% of V_DD, unless otherwise noted.
(2) Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin
low for eight clock cycles, releases the pin and samples the pin level four cycles later to
determine the source of the interrupt. (See Section 5.)
(3) To guarantee an external reset vector.
(4) This is the minimum input time; it can be pre-empted by an internal reset.
(5) The minimum period t_ILIH should not be less than the number of cycles it takes to execute the
interrupt service plus 21 t_CYC.
PA[3:0]⁽¹⁾
PA[3:0]⁽²⁾
PW_TIM
PA7^{(1), (3)}
PA7^{(2), (3)}
Notes
(1) Rising edge sensitive input.
(2) Falling edge sensitive input.
(3) Maximum pulse accumulator clocking rate is E clock frequency divided by two (E/2).
Figure A-2 Timer inputs
A
MC68HC11KW1
ELECTRICAL SPECIFICATIONS
A-5