MC68HC11KW1 Datasheet, PDF (151/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

8.5.3 SPDR — SPI data register
SPI data (SPDR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$002A (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) undefined
The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this
register initiates transmission or reception of a byte, and this only occurs in the master device. At
the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave
devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte
that caused the overrun, the first SPIF must be cleared by the time a second transfer of data from
the shift register to the read buffer is initiated.
SPI is double buffered in and single buffered out.
8.5.4 OPT2 — System configuration options register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
System config. options 2 (OPT2) $0038 LIRDV CWOM 0 IRVNE LSBF SPR2 XDV1 XDV0 000x 0000
8
LIRDV — LIR driven (refer to Section 4)
1 (set) – Enable LIR drive high pulse.
0 (clear) – LIR not driven high on MODA/LIR pin.
CWOM — Port C wired-OR mode (refer to Section 6)
1 (set) – Port C outputs are open-drain.
0 (clear) – Port C operates normally.
Bit 5 — Not implemented; always reads zero.
IRVNE — Internal read visibility/not E (refer to Section 4)
1 (set) – Data from internal reads is driven out of the external data bus.
0 (clear) – No visibility of internal reads on external bus.
In single chip mode this bit determines whether the E clock drives out from the chip.
1 (set) – E pin is driven low.
0 (clear) – E clock is driven out from the chip.
MC68HC11KW1
SERIAL PERIPHERAL INTERFACE
8-9