MC68HC11KW1 Datasheet, PDF (93/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

5.1.3.1 COPRST — Arm/reset COP timer circuitry register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
COP timer arm/reset (COPRST) $003A (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) not affected
Complete the following reset sequence to service the COP timer. Write $55 to COPRST to arm
the COP timer clearing mechanism. Then write $AA to COPRST to clear the COP timer. Executing
instructions between these two steps is possible as long as both steps are completed in the
correct sequence before the timer times out.
5.1.4 Clock monitor reset
5
The clock monitor circuit is based on an internal RC time delay. If no MCU clock edges are
detected within this RC time delay, the clock monitor can optionally generate a system reset. The
clock monitor function is enabled or disabled by the CME control bit in the OPTION register. The
presence of a timeout is determined by the RC delay, which allows the clock monitor to operate
without any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the COP needs a clock to
function, it is disabled when the clocks stop. Therefore, the clock monitor system can detect clock
failures not detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout values between individual
devices. An E clock frequency below 10 kHz is detected as a clock monitor error. An E clock
frequency of 200 kHz or more prevents clock monitor errors. Use of the clock monitor function
when the E clock is below 200 kHz is not recommended.
Special considerations are needed when a STOP instruction is executed and the clock monitor is
enabled. Because the STOP function causes the clocks to be halted, the clock monitor function
generates a reset sequence if it is enabled at the time the STOP mode was initiated. Before
executing a STOP instruction, clear the CME bit in the OPTION register to zero to disable the clock
monitor. After recovery from STOP, set the CME bit to logic one to enable the clock monitor.
MC68HC11KW1
RESETS AND INTERRUPTS
5-3