MC68HC11KW1 Datasheet, PDF (196/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.7.8 PWDTY1–4 — PWM timer duty cycle registers 1 to 4
Pulse width duty 1 (PWDTY1)
Pulse width duty 2 (PWDTY2)
Pulse width duty 3 (PWDTY3)
Pulse width duty 4 (PWDTY4)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$006C (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
$006D (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
$006E (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
$006F (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 1111 1111
There is one duty register for each channel. The value in this register determines the duty cycle
of the associated PWM timer channel. PWDTYx is compared to the counter contents and if they
are equal, a match occurs and the output goes to the state defined by the associated polarity bit.
If the register is written while the channel is enabled, then the new value is held in a buffer until
the counter rolls over or the channel is disabled. Reads of this register return the most recent value
written.
Note:
If PWDTYx ≥ PWPERx then there will be no change of state due to the duty cycle value.
In addition, if the duty register is set to $00, then the output will always be in the state
which would normally be result from the duty change of state (see also
Section 9.7.9).
PWMx
9
PWDTYx
PWPERx
Figure 9-7 PWM duty cycle
9.7.9 Boundary cases
The following boundary conditions apply to the values stored in the PWDTYx and PWPERx
registers and the PPOLx bits:
• If PWDTYx = $00, PWPERx > $00 and PPOLx = 0 then the output is always high.
• If PWDTYx = $00, PWPERx > $00 and PPOLx = 1 then the output is always low.
• If PWDTYx ≥ PWPERx and PPOLx = 0 then the output is always low.
• If PWDTYx ≥ PWPERx and PPOLx = 1 then the output is always high.
• If PWPERx = $00 and PPOLx = 0 then the output is always low.
• If PWPERx = $00 and PPOLx = 1 then the output is always high.
9-44
TIMING SYSTEM
MC68HC11KW1