MC68HC11KW1 Datasheet, PDF (61/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

CR[1:0] — COP timer rate select bits (refer to Section 5)
These control bits determine a scaling factor for the watchdog timer.
4.3.2.5 OPT2 — System configuration options register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
System config. options 2 (OPT2) $0038 LIRDV CWOM 0 IRVNE LSBF SPR2 XDV1 XDV2 000x 0000
4
LIRDV — LIR driven
1 (set) – Enable LIR drive high pulse.
0 (clear) – LIR not driven high on MODA/LIR pin.
In single-chip and bootstrap modes, this bit has no meaning or effect. The LIR pin is driven low to
indicate that execution of an instruction has begun. The LIR pin is normally configured for
wired-OR operation (only pulls low). In order to detect consecutive instructions in a high-speed
application, this signal can be made to drive high for a quarter of a cycle to prevent false triggering
(LIRDV set).
CWOM — Port C wired-OR mode (refer to Section 6)
1 (set) – Port C outputs are open-drain.
0 (clear) – Port C operates normally.
Bits [5, 0] — Not implemented; always read zero.
IRVNE — Internal read visibility/not E
IRVNE may be written once in normal modes, and can be written as often as desired in bootstrap
and special test modes. In special test modes, IRVNE is reset to one. In normal and bootstrap
modes, IRVNE is reset to zero. IRVNE should only be used at room temperature and 5V nominal.
In expanded modes, IRVNE determines whether internal read visibility (IRV) is on or off.
1 (set) – Data from internal reads is driven out of the external data bus.
0 (clear) – No visibility of internal reads on external bus.
In single chip modes this bit determines whether the E clock drives out from the chip.
1 (set) – E pin is driven low.
0 (clear) – E clock is driven out from the chip.
Refer to the following table for a summary of the operation immediately following reset.
MC68HC11KW1
OPERATING MODES AND ON-CHIP MEMORY
4-17