MC68HC11KW1 Datasheet, PDF (174/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

T2STP — Stop Timer 2 counter
1 (set) – Timer 2 counter and prescaler are stopped and the counter is reset
to $0000.
0 (clear) – Timer 2 counter operates normally.
I1/O4 — Input capture 1/output compare 4
1 (set) – Input capture 1 function is enabled (no OC4)
0 (clear) – Output compare 4 function is enabled (no IC1)
9.2.9 T2MSK — Timer 2 interrupt mask register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer 2 interrupt mask (T2MSK) $008C OC1I OC2I OC3I C4I TO2I 0
0
0 0000 0000
Use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts.
Note:
Bits in T2MSK correspond bit for bit with flag bits in T2FLG. Ones in T2MSK enable the
corresponding interrupt sources.
OC1I–OC3I — Output compare x interrupt enable
9
1 (set) – OC interrupt is enabled.
0 (clear) – OC interrupt is disabled.
If an OCxI enable bit is set when its associated OCxF flag bit is set, a hardware interrupt sequence
is requested. All three interrupt enable bits are associated with a single Timer 2 output compare
interrupt sequence; any successful output compare causes such an interrupt unless the
corresponding OCxI bit is clear. Therefore, flag polling is required unless all but one of the
interrupts have been disabled.
C4I— Input capture 1/output compare 4 interrupt enable
1 (set) – IC1/OC4 interrupt is enabled.
0 (clear) – IC1/OC4 interrupt is disabled.
When I1/O4 in TCTL4 is set, C4I is the input capture 1 interrupt enable bit.
When I1/O4 in TCTL4 is zero, C4I is the output compare 4 interrupt enable bit.
9-22
TIMING SYSTEM
MC68HC11KW1