MC68HC11KW1 Datasheet, PDF (175/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

TO2I — Timer 2 overflow interrupt enable
1 (set) – Timer 2 overflow interrupt requested when T2OF is set.
0 (clear) – T2OF interrupts disabled.
Bits [2:0] — Not implemented; always read zero.
9.2.10 T2FLG — Timer 2 interrupt flag register
Timer 2 interrupt flag (T2FLG)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$008D OC1F OC2F OC3F C4F TO2F 0
0
0 0000 0000
Bits in this register indicate when timer system events have occurred. Clear flags by writing a one
to the corresponding bit position(s).
Note:
Bits in T2FLG correspond bit for bit with flag bits in T2MSK. Ones in T2MSK enable the
corresponding interrupt sources.
OC1F–OC3F — Output compare x flag
1 (set) – Counter has reached the preset output compare x value.
0 (clear) – Counter has not reached the preset output compare x value.
These flags are set each time the counter matches the corresponding output compare x values.
9
C4F — Input capture 1/output compare 4 flag
This flag is set by IC1 or OC4, depending on the function enabled by I1/O4 bit in TCTL4. If C4 is
configured as an input capture channel, then:
1 (set) – Selected edge has been detected on pin PJ7
0 (clear) – Selected edge has not been detected on pin PJ7.
TO2F — Timer 2 overflow flag
1 (set) – TCNT2 has overflowed from $FFFF to $0000.
0 (clear) – No Timer 2 overflow has occurred.
Bits [2:0] — Not implemented; always read zero.
MC68HC11KW1
TIMING SYSTEM
9-23